1. Field of the Invention
The present invention relates to control of a production line for semiconductor fabrication. More particularly, the present invention concerns control for a semiconductor production line that queues work-in-process (WIP) before a re-entrant bottleneck processing node (such as a photo-lithographer), with the control utilizing a push-type method for sending WIP to subsequent processing nodes for processing after a determination has been made that a cleared trajectory through all subsequent processing nodes back to the re-entrant process is available and after the subsequent processing nodes have been reserved for the trajectory.
2. Description of the Related Art
Semiconductor fabrication is generally performed in a re-entrant production line consisting of a network of processing nodes. The production line is re-entrant in that a single WIP is processed multiple times by at least one of the processing nodes, usually a photolithography node. Due to a lack of control over WIP entering a queue for the re-entrant node, the re-entrant node often becomes a bottleneck in the processing network. The bottleneck results in inefficiencies in the production line utilization; inefficiencies that result in increased cost of both ownership and operation of the production line.
Additionally, subsequent processing nodes following the photolithography node can decrease the efficiency of the production line. These subsequent processing nodes perform manufacturing functions such as implantation, etching, metrology, oxidation, and so forth. Given the small amount of control over the actual WIP and these subsequent processing nodes, secondary bottlenecks can form in the production line leading to further inefficiencies. In addition, re-tooling and setup times of the various process machinery at the nodes can further increase the inefficiency.
These inefficiencies increase the cost of ownership and operation of the entire network. Therefore, maximizing the utilization of the bottleneck process, as well as reducing secondary bottlenecks, would improve the throughput of the network as a whole and minimize the cost of ownership.
Unfortunately, developing an optimal schedule for such a production facility can be very complex due to the number of steps involved and the possible combinations of those steps. Due to the complex computations involved in developing a schedule, real-time adjustments to the schedule can be very difficult.
Some effort has been made to resolve this problem and to increase the throughput of the production line. For example, U.S. Pat. No. 5,889,673, entitled xe2x80x9cManufacturing Method And System For Dynamic Dispatching Of Integrated Circuit Wafer Lotsxe2x80x9d, utilizes a method for dynamic dispatching of integrated circuit wafer lots (product). According to the patent, loading factors of machines downstream of the lithography machine, or descendent machines, are calculated to determine the machine with the lowest estimated loading value. That machine is then given the highest priority and the wafer lots are dispatched to that machine after the lithography process.
Therefore, the method of U.S. Pat. No. 5,889,673 addresses selection of which machine the product is sent to after the lithography process, in order to ensure that each downstream machine is adequately loaded. However, this method does not guarantee that the product will be processed by each downstream machine immediately upon the product arriving at the machine. As a result, secondary bottlenecks are still likely to occur.
Another attempt to reduce secondary bottlenecks is described in U.S. Pat. No. 5,446,671, entitled xe2x80x9cLook-Ahead Method For Maintaining Optimum Queued Quantities Of In-Process Parts At A Manufacturing Bottleneckxe2x80x9d. According to the patent, a look-ahead method monitors the product queued in all potential bottleneck processing nodes in the factory. A flag status is set at the queue of each potential bottleneck process to prevent product from being started until the queue at the bottleneck process has declined to a sufficiently low point as determined by factory management personnel. Thus product pile-up at the bottleneck queues is reduced.
However, like U.S. Pat. No. 5,889,673, the method of U.S. Pat. No. 5,446,671 also does not guarantee that the product will be processed through all processing nodes immediately upon receipt of the product at the node. Thus, with this method a secondary bottleneck is still present with the amount of product in the bottleneck queue having merely been reduced.
The importance of addressing bottleneck queues is particularly illustrated in the process of manufacturing semiconductors. Generally, in a semiconductor manufacturing facility, a semiconductor is produced by an initial product, such as a single wafer, being processed through a series of processing nodes to form a finished product. Each processing node in the series generally performs a different processing task. For example, the manufacturing facility may contain a series of processing nodes where each node is respectively dedicated to performing lithography, implantation, etching, metrology, or oxidation. The processing through each process may be linear with any particular process or processing node being visited only once. Alternatively, there may be a series of loops where a wafer is routed through the same processing node multiple times. The linear model is typical of a manufacturing production line where processing nodes or processes are set out in a definite order, while the loop model is typical of a production line where processing nodes are used as needed, depending upon the product. In the latter case, the product being processed may be re-entrant into the conceptual production line if one machine is used more than once.
In the present invention, one possible production method concerns a general network of processing nodes with no restrictions on the order of processing or the number of processes needed to finish a job. Also, no restriction is placed on the number or type of entry or exit nodes in the network. In a limiting case, a route through an isolated network of n nodes is equivalent to routes covering a complete directed graph (digraph) of N vertices and N(Nxe2x88x921) edges. A dynamic path through multiple nodes from one defined node to another defined node is referred to as a trajectory T(j,tj), where j is an ordered set of nodes and tj is a set of arrival times.
In a series of processing nodes, at least one type of processing node will generally be a bottleneck. The bottleneck may exist for a variety of reasons. For example, the length of a task being performed at the node may be longer than other processes or the node may be revisited multiple times. Also the cost of the bottleneck processor and/or the cost of operating the bottleneck processor may be very expensive, thereby limiting the number of those processors that may be employed in the network. Therefore, the cost of operating the processing network could be somewhat minimized by maximizing utilization of the bottleneck process. That is, improving the throughput of the bottleneck process would improve the throughput of the network as a whole, thereby reducing the cost of ownership of the entire network. However, improving the throughput of the bottleneck process alone may not lower the cost of ownership of the entire network where, for example, there is extreme under-utilization of less expensive processors.
Many manufacturing networks are finite source queuing networks where jobs are added to the system by considering the maximum number of jobs in the system. A description of finite source queuing networks can be found in Xiuli Chao, et al., xe2x80x9cQueuing Networks: Customers, Signals and Product Form Solutionsxe2x80x9d, pp. 219-221, 1999, Wiley. Under these circumstances, the arrival rate may be defined as:
xcex(n)=0 for nxe2x89xa7Mxe2x80x83xe2x80x83(1)
xcex(n) is positive and finite for nxe2x89xa6Mxe2x88x921, where M is a positive integer. In this case, M is the number of jobs the system can hold.
The stationary distribution of the system, or the average number of jobs in the system, is determined by the marginal distribution of the stationary distributions at the nodes of the system.                               π          ⁡                      (                          n              _                        )                          =                              c            ⁢                                          ∏                                  j                  =                  0                                N                            ⁢                              xe2x80x83                            ⁢                                                                    π                    j                                    ⁡                                      (                                          n                      j                                        )                                                  ⁢                                  xe2x80x83                                ⁢                for                ⁢                                  xe2x80x83                                ⁢                                                      ∑                                          j                      =                      0                                        N                                    ⁢                                      xe2x80x83                                    ⁢                                      n                    j                                                                                =          M                                    (        2        )            
One may expect that the stationary distribution at each node of a system having multiple processing nodes will be approximately Poisson in form, and thus, the joint distribution of all of the processing nodes will also be Poisson in form. Assuming that the balance rate equations hold in an operational system, and thus the throughput of an individual node is equal to the arrival rate, the throughput of the individual nodes can be related to the queue length or the number of jobs. Assuming a Poisson distribution for the arrival rate, a utilization factor, xcfx81j for any node j, can be related to the average number of jobs, nj, at the node by the formula,                               ρ          j                =                              n            j                                (                                          n                j                            +              1                        )                                              (        3        )            
Where an average utilization of 66% is desired for each node, the average number of jobs at each node must be 2. Therefore, for the total average utilization of the network to be 66%, from equation (2), the network needs an average of 2n jobs. However, since arrival at each node is a Poisson process, a buffer must be available at each node. For example, if on average there are two jobs at each node, for one-eighth of the time, there will be a queue with four jobs waiting to be processed at any node and there is a 1:100 chance that 10 jobs will be queued.
Buffering in a product queue is an important part of managing the network. Buffering can be achieved either by a central buffer, that is after processing, the jobs can be returned to one buffer, or the buffering can be spread amongst the various processing nodes, depending on the actual probability of them being used. The details of the distribution of buffers depends on the mix of process times and schedules of the job processing. The buffering discipline chosen will also take into account the difficulty and time constraints of moving the processed jobs. For both the linear model and the re-entrant model, this distribution of buffering and scheduling of delivery of product to a processing node can be a complex problem and can add significantly to processing times and labor costs.
The above utilization calculation of the processing nodes assumes that there is no setup time for the job on the processing equipment. That is, the process node, when idle, is able to instantly begin processing upon arrival of a job. If this condition is not true, then the utilization of the equipment drops. This is true even if setup time can be done concurrently with the processing of a previous job. In this case, utilization falls rapidly unless the average number of waiting jobs is increased. If the setup time is similar to the process time, then the node must have, on average, four jobs, one running and one being concurrently set up, in order to achieve 60-70% utilization. Thus, even a network with concurrent setup time increases both the work in process and the buffering problem. There are no general solutions for these problems, and specific solutions are computationally intensive and do not have a built in cost of ownership factor.
Therefore, the buffering (or queuing) at the bottleneck process is one determining process for both the throughput of the network and the capacity of the system. Accordingly, improving this process would facilitate a lowered cost of ownership of the network.
The present invention addresses the foregoing by providing control over a production line that queues work-in-process (WIP) before a re-entrant bottleneck processing node. The invention utilizes a push-type method for sending WIP from the bottleneck process to subsequent processing nodes, after confirming that a cleared trajectory exists through all processing nodes back to the re-entrant processing node or out to exit, and after reserving the cleared trajectory for the WIP in question.
In one aspect, the invention may be embodied in the context of a production line such as a semiconductor production line, where product such as a single wafer or a cassette of wafers, are queued in a pre-lithography queue awaiting processing. In order to provide for more efficient utilization of the production line, flow of product through the production line is controlled by determining that a cleared trajectory through all processing nodes subsequent to the bottleneck processing node (lithography) is available. Once a cleared trajectory has been found, the subsequent processing nodes are reserved for the cleared trajectory and the WIP in question. A WIP is then selected from the re-entrant queue for the trajectory and then the trajectory is initiated. The trajectory preferably includes either a trajectory back to the queue or to an exit of the production line.
As a result of the foregoing, WIP selected for the trajectory is processed through each processing node in the production line upon receipt of the product by each node. Therefore, secondary bottlenecks are largely avoided because the product processing has been pre-reserved at each node and there is ordinarily no need for product to wait for the node to become available. Accordingly, the invention provides for more efficient utilization of the production line and a reduction in secondary bottlenecks.
In further aspects of the invention, where multiple WIP""s qualify for initiation of their respective trajectories, one WIP is selected over the others based on a queuing discipline, such as priority of jobs.
The invention may be embodied in the foregoing method or apparatus. An apparatus according to the invention controls a production line that queues WIP prior to a re-entrant bottleneck process. The apparatus may comprise a memory for storing executable process steps, and a processor for executing the executable process steps, wherein the executable process steps comprise a cleared trajectory determination and processing node reservation for the trajectory corresponding substantially to the foregoing method.
Further embodiments of the invention include computer-executable process steps or a computer-readable medium on which is stored code for performing the computer-executable process steps, wherein the process steps comprise a cleared trajectory determination and processing node reservation corresponding substantially to the aforementioned method.
In yet another aspect, the present invention may be a method to schedule a process job consisting of multiple processing steps through a network of multiple processing nodes. Prior to describing the method, a bottleneck processing node must be defined and a product buffer must be available at the bottleneck node. Therefore, defining a node or node type that is the main bottleneck process or a process used for setting up the bottleneck process in a multi-node processing network is first accomplished. Once the bottleneck node is defined, a product buffer is arranged on the bottleneck node for containing a queue.
To begin the method, a product is selected from the queue to be processed. The product may be selected based on some queuing discipline such as priority of jobs in the queue. However, before processing of the product by the bottleneck process begins, a determination is made whether there is a cleared trajectory through all processing nodes subsequent to the bottleneck node that are necessary for processing the product. The trajectory may be either to the next bottleneck processing node buffer, or to an exit of the network. Once a cleared trajectory is found, the subsequent processing nodes are reserved for the trajectory. The trajectory may be either reserved for immediate initiation, or reserved in time. After the subsequent processing nodes have been reserved, the trajectory is initiated and processing of the selected product by the bottleneck process begins. Finally, the product is either returned to the bottleneck processing node queue or to an exit of the network, depending on the state of processing for the product.
Two concepts of the invention become apparent from the foregoing method. First, a guaranteed path to either return to the bottleneck buffer or to an exit of the network is reserved. Second, a more optimal loading of the bottleneck process results. In guaranteeing a path to the pre-bottleneck buffer, the method ensures that the bottleneck processes are kept well loaded for any total loading of the network. Ensuring the bottleneck process is well loaded ensures that the network is operating at more efficient speed for any combination of processors.
This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof in connection with the attached drawings.